Xilinx Design Summary

MINIUART Partition Summary
No partition information was found.

Device Utilization Summary
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	446	27,392	1%
Number of 4 input LUTs	1,759	27,392	6%
Logic Distribution
Number of occupied Slices	1,061	13,696	7%
Number of Slices containing only related logic	1,061	1,061	100%
Number of Slices containing unrelated logic	0	1,061	0%
Total Number of 4 input LUTs	1,870	27,392	6%
Number used as logic	1,759
Number used as a route-thru	110
Number used as Shift registers	1
Number of bonded IOBs	14	556	2%
IOB Flip Flops	3
Number of PPC405s	0	2	0%
Number of Block RAMs	117	136	86%
Number of GCLKs	6	16	37%
Number of DCMs	2	8	25%
Number of GTs	0	8	0%
Number of GT10s	0	0	0%
Total equivalent gate count for design	7,698,208
Additional JTAG gate count for IOBs	672

Performance Summary
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met